In the processing of integrated circuits, electrical contact must be made to isolated active-device regions formed within a wafer/substrate. The active-device regions are connected by high electrically conductive paths or lines which are fabricated above an insulator material, which covers the substrate surface. To provide electrical connection between the conductive path and active-device regions, an opening in the insulator is provided to enable the conductive film to contact the desired regions. Such openings are typically referred to as contact openings, or simply "contacts".
As transistor active area dimensions approached one micron in diameter, conventional process parameters resulted in intolerable increased resistance between the active region or area and the conductive layer. A principal way of reducing such contact resistance is by formation of a metal silicide atop the active area prior to application of the conductive film for formation of the conductive runner. One common metal silicide material formed is TiSi.sub.x, where x is predominately "2". The TiSi.sub.x material is typically provided by first applying a thin layer of titanium atop the wafer which contacts the active areas within the contact openings. Thereafter, the wafer is subjected to a high temperature anneal. This causes the titanium to react with the silicon of the active area, thus forming the TiSi.sub.x. Such a process is said to be self-aligning, as the TiSi.sub.x is only formed where the titanium metal contacts the silicon active regions. The applied titanium film everywhere else overlies an insulative, and substantially non-reactive SiO.sub.2 layer.
Such is illustrated in FIG. 1. Shown is a semiconductor wafer 10 comprised of a bulk substrate 12 having an active area 14 formed therein. An overlying layer 16 of insulating material, predominately SiO.sub.2 in the form of BPSG, has been provided atop substrate 12 and appropriately etched to form a contact opening 18 to active area 14. A thin layer 20 of titanium is applied over insulating layer 16 and contacts active area 14. The high temperature anneal step is conducted in an inert environment, such as argon, to react titanium metal contacting active region 14 into TiSi.sub.x, thereby forming the illustrated TiSi.sub.x region 22. The remaining portion of layer 20 not contacting region 14 is substantially nonreactive with its underlying insulating SiO.sub.2 layer 16, and thereby remains as elemental titanium metal.
A contact filling material, such as tungsten, is typically applied atop silicide region 22. Tungsten adheres poorly to TiSi.sub.x. To overcome this problem, an intervening layer typically of TiN is interposed between silicide region 22 and an overlying tungsten layer. TiN is commonly referred to as a "glue layer" for the metal tungsten layer. Such can be provided by annealing wafer 10 with titanium layer 20 in an atmosphere which is predominately nitrogen. Under such conditions, the lower portion of layer 20 overlying active region 14 will react with the silicon to form the TiSi.sub.x, while the upper portion of layer 20 of the titanium over contact area 14 and the remaining portion of layer 20 over insulating material 16 reacts with the nitrogen of the atmosphere to form TiN.
From this point, the predominate conductive material of the runner to be formed is applied. The silicide region 22 which is formed is highly conductive, and provides less electrical resistance between the runner and active area 14 than were silicide region 22 not present. Formation of such silicides, and titanium silicide in particular, are described in Wolf, et al., "Silicon Processing For The VLSI Era. Vol. 2--Process Integration," pages 143-150.
As device dimensions continue to shrink and the contact openings become deeper and narrower, contact walls become vertical and most of the metal deposition techniques fail to provide the necessary step coverage to create adequate contact with the active area 14. Such is illustrated in FIG. 2. There, active area 14a of substrate 12a is shown significantly smaller than active area 14 in FIG. 1. Correspondingly, a significantly narrower contact opening 18a is provided to active area 14, thereby maximizing circuit density. As is apparent, the ratio of the depth of contact opening 18a relative to its width is greater than the ratio of the depth to the width of contact opening 18 in FIG. 1. Such narrow, high aspect ratio contact openings 18a can result in layer 20a failing to make significant contact with region 14a, as shown. Accordingly, the desired TiSi.sub.x and electrical contact are not formed,
TiSi.sub.x can be deposited directly as opposed to a result of substrate reaction with elemental titanium. One way is by low pressure chemical vapor deposition using titanium tetrachloride and silane according to the following formula: EQU TiCl.sub.4 +2SiH.sub.4 .fwdarw.TiSi.sub.2 +4HCl+2H.sub.2 +by-products
Low pressure chemical vapor deposition provides a distinct advantage of excellent conformality adequate to achieve desired coverage in high aspect ratio vias or contacts. However, one significant problem associated with the above reaction is that it is conducted at temperatures above 700.degree. C. to effect the desired reaction. Most commercially available chemical vapor deposition reactors are comprised of aluminum, which has a melting temperature of around 600.degree. C. Accordingly, alternate material and accordingly more expensive chemical vapor deposition chambers would need to be developed for the above reaction to prevent reactor meltdown.
Another drawback associated with high temperature deposition of titanium silicide films relates to a competing reaction of the TiCl.sub.4 with silicon of the substrate. Such a reaction would compete with the low pressure chemical vapor deposition reaction, resulting in undesirable or uncontrollable consumption of silicon from the substrate.
Another prior art process of providing a titanium silicide film is disclosed in U.S. Pat. No. 4,568,565. Such discloses use of titanium halides and hydrosilicides, also referred to as silanes. However, the process requires the use of high intensity light. Such has the drawback of increasing process complexity, and causes the processor to contend with attempting to achieve light uniformity throughout the reactor. Such is not an easy task. Further, step coverage especially within high aspect ratio openings can be poor in light energy CVD processes as sidewalls within such openings do not get full exposure to light Efficiency is also problematical, as is for example evident from col. 7, Ins. 19-28 of such patent.
It would be desirable to overcome these drawbacks.